Loop unrolling for processors with instruction cache.
Henri-Pierre CharlesPublished in: Algorithms and Parallel VLSI Architectures (1991)
Keyphrases
- memory hierarchy
- instruction set
- computing power
- embedded processors
- cache misses
- memory subsystem
- main memory
- secondary storage
- multithreading
- memory access
- multiprocessor systems
- computer architecture
- database operations
- speculative execution
- floating point
- parallel algorithm
- index structure
- memory management
- data access
- database systems
- transactional memory
- multimedia