A High-Speed Hardware Architecture for Universal Message Authentication Code.

Bo Yang Ramesh Karri David A. McGrew

Published in: IEEE J. Sel. Areas Commun. (2006)

Keyphrases

hardware architecture
high speed
hardware implementation
hardware architectures
email
source code
associative memory
low power
field programmable gate array
real time
information systems
signal processing
efficient implementation
processing elements
user authentication
case study
block matching motion estimation