Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors.
Gustavo M. SantanaGuilherme PaimLeandro M. G. RochaRenato NeuenfeldMateus Beck FonsecaEduardo A. C. da CostaSergio BampiPublished in: ICECS (2017)
Keyphrases
- low power
- hardware architecture
- high speed
- logic circuits
- low cost
- power consumption
- single chip
- real time
- image sensor
- vlsi architecture
- sensor networks
- vlsi circuits
- gate array
- hardware architectures
- power reduction
- low power consumption
- cmos technology
- power dissipation
- digital signal processing
- computational power
- mixed signal
- hardware implementation
- efficient implementation
- image processing