DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs.
Jacob T. GrycelRobert J. WallsPublished in: ISCAS (2020)
Keyphrases
- field programmable gate array
- hardware implementation
- hardware software
- hardware architecture
- parallel architectures
- hardware design
- fpga technology
- reconfigurable hardware
- real time
- fpga implementation
- hardware and software
- embedded systems
- efficient implementation
- software implementation
- low cost
- parallel implementation
- software architecture
- dedicated hardware
- pipeline architecture
- vlsi architecture
- central processor
- smart camera
- memory management
- secret key
- software systems
- lightweight
- image processing