An FPGA/HMC-Based Accelerator for Resolution Proof Checking.

Tim Hansmeier Marco Platzner David Andrews

Published in: ARC (2018)

Keyphrases

field programmable gate array
automatic theorem proving
hardware implementation
theorem proving
low resolution
consequence finding
fpga implementation

embedded systems
high speed
parallel computing
real time image processing
linear logic
parallel implementation
image processing algorithms

theorem prover
hardware architecture
hardware design
low power consumption
multilabel classification
verilog hdl
mathematical proofs

real time
sampling rate
computing systems
efficient implementation
image processing
genetic algorithm
data sets