A Content - Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique.
Tanja HarbaumMatthias Norbert BalzerMarc WeberJürgen BeckerPublished in: SoCC (2018)
Keyphrases
- pattern recognition
- hardware implementation
- hardware architecture
- hardware design
- signal processing
- content management
- fpga implementation
- real time
- parallel architecture
- memory management
- image processing
- dedicated hardware
- computer vision
- management system
- image analysis
- processing elements
- parallel hardware
- fpga technology
- software implementation
- digital signal processors
- neural network
- metadata
- software architecture
- machine learning
- associative memory
- feature extraction
- level parallelism
- learning capabilities
- systolic array
- hardware architectures
- xilinx virtex
- real time image processing
- web content
- multimedia content
- data compression
- field programmable gate array
- random access
- parallel algorithm
- peer to peer
- instruction set
- fuzzy sets
- information presentation
- memory hierarchy
- low cost
- pattern recognition problems
- compressed data
- computational power