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A Memetic Algorithm Based PVT Variation-Aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design.

Mohammed Salman AhmedZia Abbas
Published in: ICCD (2019)
Keyphrases
  • memetic algorithm
  • power dissipation
  • power consumption
  • optimal design
  • circuit design
  • tabu search
  • low power
  • high speed
  • lower bound
  • differential evolution
  • assembly line balancing
  • phase locked loop