Design of a low power LNA circuit with noise canceling approach in 90 nm CMOS process.
Vikram SinghManoj KumarNitin KumarPublished in: Integr. (2024)
Keyphrases
- low power
- cmos technology
- logic circuits
- high speed
- nm technology
- power reduction
- power consumption
- gate array
- power dissipation
- low cost
- single chip
- low power consumption
- vlsi architecture
- mixed signal
- digital signal processing
- vlsi circuits
- low voltage
- circuit design
- high power
- real time
- wireless transmission
- energy dissipation
- signal to noise ratio
- ultra low power