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Evaluation of a True Random Number Generator Utilizing Timing Jitters in RSFQ Logic Circuits.
Kenta Sato
Naonori Sega
Yuta Somei
Hiroshi Shimada
Takeshi Onomi
Yoshinao Mizugaki
Published in:
IEICE Trans. Electron. (2022)
Keyphrases
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asynchronous circuits
logic circuits
low power
random number generator
delay insensitive
high speed
random number
power consumption
image processing
pattern recognition
low cost
model checking
functional decomposition
gate array