An improved phase digitization mechanism for fast-locking low-power all-digital PLLs.
Lin-Lin XieYang WangShushan QiaoYong HeiPublished in: IEICE Electron. Express (2017)
Keyphrases
- low power
- mixed signal
- power consumption
- low cost
- high speed
- single chip
- vlsi circuits
- high power
- wireless transmission
- multi channel
- low power consumption
- digital signal processing
- logic circuits
- vlsi architecture
- database systems
- image sensor
- digital data
- cmos technology
- cmos image sensor
- concurrency control
- signal processing