Low Power Hardware Architecture for Sampling-free Bayesian Neural Networks inference.
Antonios-Kyrillos ChatzimichailCharalampos AntoniadisNikolaos BellasYehia MassoudPublished in: ISCAS (2023)
Keyphrases
- low power
- hardware architecture
- neural network
- markov chain monte carlo
- low cost
- power consumption
- high speed
- associative memory
- bayesian networks
- bayesian inference
- hardware implementation
- hardware architectures
- single chip
- high power
- field programmable gate array
- pattern recognition
- logic circuits
- artificial neural networks
- low power consumption
- cmos technology
- wireless transmission
- posterior distribution
- vlsi architecture
- image sensor
- digital signal processing
- vlsi circuits
- ultra low power
- parallel algorithm
- delay insensitive
- power reduction
- software engineering
- source code
- graphical models