The VLSI architecture of a highly efficient configurable pre-processor for MIMO detections.

Tzu-Ting Tseng Chung-An Shen

Published in: IPCCC (2017)

Keyphrases

distributed memory
highly efficient
vlsi architecture
low complexity
vlsi implementation
low power
low cost
real time
multithreading
communication systems
computational complexity
fading channels
computer vision
power consumption
high speed
mode decision
multiscale