An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing.

Aydin O. Balkan Gang Qu Uzi Vishkin

Published in: DAC (2008)

Keyphrases

parallel processing
high throughput
single chip
cmos image sensor
parallel computers
parallel architectures
microarray
low power
low cost
interconnection networks
data acquisition
parallel algorithm
computer vision
load balancing
routing algorithm
parallel architecture