Performance improvement of timing and power variations due to random dopant fluctuation in negative-capacitance CMOS inverters.
Kai ZhangWeifeng LüPeng SiZhifeng ZhaoTianyu YuPublished in: IET Circuits Devices Syst. (2020)
Keyphrases
- power consumption
- low power
- high speed
- power dissipation
- chip design
- low cost
- positive and negative
- significant improvement
- cmos technology
- case study
- vlsi circuits
- wireless sensor networks
- randomly generated
- power management
- power distribution
- hd video
- delay insensitive
- real time
- asynchronous circuits
- digital signal processing
- evolutionary algorithm
- neural network
- data sets