Hardware Implementation of a Latency-Reduced Sphere Decoder With SORN Preprocessing.
Moritz BärthelSimon KnobbeJochen RustSteffen PaulPublished in: IEEE Access (2021)
Keyphrases
- hardware implementation
- preprocessing
- fpga implementation
- efficient implementation
- dedicated hardware
- signal processing
- hardware architecture
- hardware design
- image processing algorithms
- software implementation
- fpga technology
- response time
- field programmable gate array
- pipeline architecture
- parallel architecture
- memory management
- low cost
- feature extraction
- image binarization
- face recognition