Hardware Architecture for Reducing Worst-Case Latency in Fast SCF Polar Decoders.

Useok Lee Jeahack Lee Myung Hoon Sunwoo

Published in: IEEE Access (2023)

Keyphrases

hardware architecture
worst case
hardware implementation
average case
upper bound
hardware architectures
lower bound
np hard
frequency domain
associative memory
field programmable gate array
power reduction
case study
pattern recognition
processing elements
support vector