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Tunneling transport in WSe2-MoS2 heterojunction transistor enabled by a two-dimensional device architecture.

Phanish ChavaKenji WatanabeTakashi TaniguchiThomas MikolajickManfred HelmArtur Erbe
Published in: DRC (2022)
Keyphrases
  • three dimensional
  • multi dimensional
  • management system
  • high speed
  • real time
  • data sets
  • layered architecture
  • space charge
  • integrated circuit
  • design considerations
  • input device
  • equivalent circuit