Variation-resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency.
Nele ReyndersWim DehaenePublished in: ESSCIRC (2012)
Keyphrases
- cmos technology
- clock frequency
- low power
- high speed
- digital signal processors
- field programmable gate array
- power consumption
- ultra low power
- power dissipation
- hardware implementation
- high end
- parallel processing
- low cost
- massively parallel
- real time
- parallel architecture
- embedded systems
- information systems
- computer vision