Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT.

C. Lu C. H. Lee T. Nishimura A. Toriumi

Published in: VLSIC (2015)

Keyphrases

cmos technology
neural network
user interface
design process
machine learning
information retrieval
information systems
knowledge base
multiscale
expert systems
building blocks
computer aided
design space
nm technology