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Energy and Delay Tradeoffs of Soft-Error Masking for 16-nm FinFET Logic Paths: Survey and Impact of Process Variation in the Near-Threshold Region.

Faris S. AlgharebRizwan A. AshrafAhmad AlzahraniRonald F. DeMara
Published in: IEEE Trans. Circuits Syst. II Express Briefs (2017)
Keyphrases
  • neural network
  • input image
  • logic programming
  • region of interest
  • knowledge base
  • data collection
  • shortest path
  • error rate
  • process model
  • steady state
  • cost benefit