A consistency-free memory architecture for sort-last parallel rendering processors.
Woo-Chan ParkCheong-Ghil KimDuk-Ki YoonKil-Whan LeeIl-San KimTack-Don HanPublished in: J. Syst. Archit. (2007)
Keyphrases
- processing elements
- inter processor communication
- multithreading
- parallel architecture
- level parallelism
- parallel algorithm
- parallel computers
- single instruction multiple data
- parallel processing
- load balancing
- shared memory
- multiprocessor systems
- massively parallel
- memory hierarchy
- processor array
- parallel computing
- distributed memory
- associative memory
- hardware architecture
- memory access
- real time
- instruction set
- multi processor
- random access
- parallel processors
- cluster of workstations
- single processor
- parallel computation
- distributed processing
- data transfer
- multi core processors
- computer architecture
- compute intensive
- memory bandwidth
- master slave
- parallel architectures
- hardware implementation
- processing units
- high quality
- parallel execution
- parallel version
- message passing interface
- load balance
- memory management
- parallel implementation
- parallel programming
- computational power
- memory subsystem
- data parallelism
- high performance computing
- management system
- computer graphics
- database systems