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An 180 nm CMOS 1.84-to-3.62 GHz fractional-N frequency synthesizer with skewed-reset PFD for removing noise-folding effect.
Sang-Geun Bae
Kyeong-Woo Kim
In-Chul Hwang
Published in:
IEICE Electron. Express (2014)
Keyphrases
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removing noise
high speed
power consumption
cmos technology
low cost
dielectric constant
denoising
low power
silicon on insulator
image denoising
metal oxide semiconductor