A multiple clocking scheme for low power RTL design.

Christos A. Papachristou Mark Spining Mehrdad Nourani

Published in: ISLPD (1995)

Keyphrases

low power
single chip
power consumption
low cost
high speed
power dissipation
logic circuits
low power consumption
vlsi architecture
cmos technology
gate array
vlsi circuits
mixed signal
circuit design
power reduction
real time
digital signal processing
design process
high power
ultra low power