Login / Signup
Runtime Congestion and Crosstalk Aware Router for FPGA Using Jbits3.0 for Partial Reconfigurable Application.
Nachiketa Das
Pranab Roy
Hafizur Rahaman
Published in:
ISED (2011)
Keyphrases
</>
real time
data sets
general purpose
hardware implementation
low cost
high speed
signal processing
end to end
hardware design
dedicated hardware
digital signal