1.2V 300MHz CMOS PLL for clock generation in 0.35UM process.

Deana McDonagh K. I. Arshak O. Abubaker

Published in: Communication Systems and Networks (2006)

Keyphrases

high speed
power consumption
generation process
cmos technology
multi agent systems
databases
data mining
learning algorithm
image processing
clustering algorithm
data structure
low cost