Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAs.

Jaafar Alghazo Nazeih Botros

Published in: CDES (2005)

Keyphrases

floating point
fixed point
square root
instruction set
interval arithmetic
sparse matrices
hardware implementation
floating point arithmetic
fast fourier transform
data fusion
three dimensional
image processing
field programmable gate array
hardware design
fpga implementation