A methodology for hardware verification using compositional model checking.
Kenneth L. McMillanPublished in: Sci. Comput. Program. (2000)
Keyphrases
- model checking
- temporal logic
- automated verification
- formal verification
- model checker
- verification method
- formal specification
- concurrent systems
- symbolic model checking
- temporal properties
- partial order reduction
- finite state
- computation tree logic
- finite state machines
- pspace complete
- formal methods
- timed automata
- bounded model checking
- reachability analysis
- transition systems
- process algebra
- linear temporal logic
- epistemic logic
- asynchronous circuits
- linear time temporal logic
- alternating time temporal logic
- reactive systems
- web services
- automated reasoning
- embedded systems
- knowledge representation