Low power hardware implementations for network packet processing elements.
M. Mohamed Asan BasiriSandeep K. ShuklaPublished in: Integr. (2018)
Keyphrases
- low power
- high speed
- content addressable memory
- power consumption
- low cost
- processing elements
- functional units
- logic circuits
- network traffic
- cmos technology
- neural network
- mixed signal
- massively parallel
- computer networks
- general purpose
- real time
- communication networks
- image processing algorithms
- random access
- cloud computing
- peer to peer
- distributed systems