Novel architecture for inverse mix columns for AES using ancient Vedic Mathematics on FPGA.
Sushma R. HuddarSudhir Rao RupanagudiRamya RaviShikha YadavSanjay JainPublished in: ICACCI (2013)
Keyphrases
- hardware architecture
- real time
- digital signal processing
- hardware implementation
- hardware design
- high speed
- parallel architecture
- fpga implementation
- software implementation
- hardware architectures
- low power
- field programmable gate array
- dedicated hardware
- xilinx virtex
- management system
- systolic array
- pipelined architecture
- software architecture
- computer science
- data flow
- reconfigurable hardware
- cryptographic algorithms
- network architecture
- low cost
- fpga technology