A low-power VLSI architecture for full-search block-matching motion estimation.
Viet L. DoKenneth Y. YunPublished in: IEEE Trans. Circuits Syst. Video Technol. (1998)
Keyphrases
- vlsi architecture
- low power
- block matching motion estimation
- efficient implementation
- low cost
- power consumption
- video coding
- high speed
- video compression
- motion estimation
- low complexity
- signal processing
- motion compensation
- real time
- motion vectors
- macroblock
- vlsi implementation
- low density parity check
- multiresolution