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Scalable Systolic Array Multiplier Optimized by Sparse Matrix.
RiMing Jia
Tu Xu
Yuchun Chang
Published in:
ASICON (2021)
Keyphrases
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sparse matrix
systolic array
floating point
reconfigurable architecture
data flow
parallel architecture
hardware implementation
image processing
fixed point
rows and columns
image segmentation
image classification
sample size