Hardware Architecture of Embedded Inference Accelerator and Analysis of Algorithms for Depthwise and Large-Kernel Convolutions.
Tse-Wei ChenWei TaoDeyu WangDongchao WenKinya OsaMasami KatoPublished in: CoRR (2021)
Keyphrases
- hardware architecture
- computational complexity
- hardware architectures
- hardware implementation
- efficient implementation
- feature space
- learning algorithm
- feature vectors
- block matching motion estimation
- signal processing
- graphical models
- general purpose
- pattern recognition
- support vector
- image segmentation
- case study
- computer vision