Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks.
Atefeh SohrabizadehYunsheng BaiYizhou SunJason CongPublished in: CoRR (2021)
Keyphrases
- neural network
- field programmable gate array
- pattern recognition
- semi automated
- graph model
- graph representation
- optimization algorithm
- graph structure
- low cost
- optimization problems
- high speed
- structured data
- self organizing maps
- neural network model
- graph theory
- parallel implementation
- optimization process
- hardware implementation
- weighted graph
- real time image processing
- bipartite graph
- hardware architecture
- connected components
- back propagation
- signal processing
- genetic algorithm
- min sum
- reconfigurable hardware
- graph theoretic
- feed forward
- directed graph
- optimization method
- random walk