A 3.2GHz-sample-rate 800mHz bandwidth highly reconfigurable analog FIR filter in 45nm CMOS.
Eoin O'hAnnaidhEmmanuel RouatSarah VerhaerenStéphane Le TualChristophe GarnierPublished in: ISSCC (2010)
Keyphrases
- cmos technology
- high speed
- fir filters
- clock frequency
- nm technology
- low power
- power consumption
- floating gate
- analog vlsi
- low cost
- focal plane
- circuit design
- vlsi implementation
- low voltage
- frequency response
- power reduction
- finite impulse response
- field programmable gate array
- filter design
- image sensor
- silicon on insulator
- hardware implementation
- filter bank
- power dissipation
- impulse response
- signal processing
- linear algebra
- analog to digital converter
- multiresolution
- image processing
- parallel computing
- image restoration