Processing time saving in low power voice coding applications using synchronous reconfigurable co-processing architecture.
Salvatore M. CartaLuigi RaffoPublished in: ICECS (2002)
Keyphrases
- low power
- low cost
- reconfigurable hardware
- vlsi architecture
- real time
- power consumption
- high speed
- power reduction
- image sensor
- mixed signal
- single chip
- high power
- cmos technology
- coding scheme
- parallel architecture
- deblocking filter
- low power consumption
- nm technology
- vlsi circuits
- hardware implementation
- hardware and software
- signal processor
- digital signal processing
- coding method
- gate array
- wireless transmission
- general purpose
- vlsi implementation
- processing elements
- signal processing