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High-Speed Virtual Logic Network on Chip Router Architecture for Various Topologies.
E. Lakshmi Prasad
M. N. Giri Prasad
A. R. Reddy
Published in:
Comput. Electr. Eng. (2018)
Keyphrases
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network on chip
high speed
routing algorithm
multi processor
network simulator
packet switched
low power
power dissipation
data transfer
shared memory
wireless sensor networks
real time
cmos technology
multipath
power consumption
single chip
data flow