A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop.
Younghyun LimJuyeop KimYongwoo JoJooeun BangJaehyouk ChoiPublished in: IEEE J. Solid State Circuits (2022)
Keyphrases
- low power
- high speed
- power consumption
- low power consumption
- low cost
- clock frequency
- digital signal processing
- high power
- single chip
- wireless transmission
- vlsi architecture
- cmos technology
- logic circuits
- dielectric constant
- vlsi circuits
- packet loss
- frequency band
- mixed signal
- real time
- power saving
- power dissipation
- data flow
- power reduction
- low frequency
- frame rate