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FPGA-based implementation of two-step schedulers for modular optical interconnection networks.

Justine Cris BorromeoIsabella CeruttiPiero CastoldiRosula S. J. ReyesNicola Andriolli
Published in: JOCN (2021)
Keyphrases
  • interconnection networks
  • multistage
  • hardware implementation
  • hardware architecture
  • probabilistic model
  • post processing
  • routing algorithm
  • image processing
  • parallel algorithm
  • hardware design