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DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction.

Dave Y.-W. LinCharles H.-P. Wen
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2020)
Keyphrases
  • error rate
  • flip flops
  • power dissipation
  • test set
  • power consumption
  • multiple input
  • low power
  • training error
  • lower error rates
  • correct recognition rate
  • lower bound
  • digital signal processing
  • word error rate