The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures.
Bianca SilveiraGuilherme PaimBrunno Alves AbreuRafael dos Santos FerreiraCláudio Machado DinizEduardo Antônio César da CostaSergio BampiPublished in: Circuits Syst. Signal Process. (2022)
Keyphrases
- low power
- hardware architectures
- logic circuits
- power dissipation
- power consumption
- low cost
- high speed
- computational power
- hardware architecture
- single chip
- high power
- wireless transmission
- digital signal processing
- gate array
- vlsi circuits
- vlsi architecture
- low power consumption
- parallel processing
- image processing
- image sensor
- linear algebra
- digital camera
- software engineering
- mixed signal
- delay insensitive
- pattern recognition
- neural network
- real time