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Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era.

George PatsilarasNiket K. ChoudharyJames Tuck
Published in: ACM Trans. Archit. Code Optim. (2012)
Keyphrases
  • level parallelism
  • memory bandwidth
  • instruction set
  • parallel processing
  • multi core processors
  • artificial intelligence
  • low cost