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Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor.
Jinli Rao
Tianyong Ao
Shu Xu
Kui Dai
Xuecheng Zou
Published in:
IEICE Trans. Inf. Syst. (2018)
Keyphrases
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single chip
efficient implementation
engineering design
neural network
case study
high speed
application specific
processor core
information systems
management system
binary images
design principles
design tools
computer architecture