A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU.
Masao NaruseTatsuya KameiToshihiro HattoriTakahiro IritaKenichi NittaTakao KoikeShinichi YoshiokaKoji OhnoMasahito SaigusaMinoru SakataYukio KodamaYuji AraiTeruyoshi KomuroPublished in: ISSCC (2008)