High speed V.32 trellis encoder/decoder implementation using FPGA.
Anh DinhRalph MasonJoe TothPublished in: ISCAS (4) (1999)
Keyphrases
- high speed
- low complexity
- fpga implementation
- distributed video coding
- hardware implementation
- video codec
- decoding process
- low power
- rate distortion
- real time
- wyner ziv video coding
- power reduction
- video coding scheme
- noisy channel
- error control
- dedicated hardware
- xilinx virtex
- wyner ziv
- hardware architecture
- frame rate
- efficient implementation
- low cost
- motion estimation
- video encoder
- turbo codes
- transform domain
- coding scheme
- image sequences