A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets.
Yao XinWenjun LiGaogang XieYang XuYi WangPublished in: IEEE Micro (2023)
Keyphrases
- rule sets
- predictive accuracy
- decision rules
- decision trees
- rule learning
- classification rules
- error rate
- rule induction
- association rules
- rule generation
- pattern recognition
- real world
- classification accuracy
- machine learning
- membership functions
- hardware design
- feature extraction
- rough set theory
- packet switching
- hardware architecture
- real time
- information retrieval
- fuzzy rules
- semi supervised
- computer vision
- learning algorithm
- classification algorithm
- hardware implementation
- learning classifier systems
- preprocessing
- data mining
- computational intelligence
- active learning
- rule learner
- high dimensional