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A High Memory Bandwidth FPGA Accelerator for Sparse Matrix-Vector Multiplication.
Jeremy Fowers
Kalin Ovtcharov
Karin Strauss
Eric S. Chung
Greg Stitt
Published in:
FCCM (2014)
Keyphrases
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sparse matrix
floating point
memory bandwidth
field programmable gate array
fixed point
level parallelism
instruction set
parallel programming
hardware implementation
processing power
signal processing
parallel computing
random projections
rows and columns