An IF-sampling timing skew-insensitive parallel S/H circuit.

Mikko Aho Väinö Hakkarainen Lauri Sumanen Mikko Waltari Kari Halonen

Published in: ISCAS (1) (2004)

Keyphrases

parallel processing
random sampling
skewed data
shared memory
high speed
data skew
neural network
monte carlo
sampling strategies
database
decision trees
parallel implementation
sampling algorithm
parallel computation
sampling strategy
analog circuits