Bit-parallel systolic multiplier over GF ( 2 m ) for irreducible trinomials with ASIC and FPGA implementations.
Sudha Ellison MatheLakshmi BoppanaPublished in: IET Circuits Devices Syst. (2018)
Keyphrases
- hardware implementation
- bit parallel
- software implementation
- efficient implementation
- pattern matching
- hardware architecture
- field programmable gate array
- general purpose processors
- hardware architectures
- fpga implementation
- xilinx virtex
- signal processing
- regular expressions
- systolic array
- hardware design
- parallel architecture
- dedicated hardware
- image processing algorithms
- single chip
- fpga technology
- application specific integrated circuits
- fpga device
- real time
- general purpose
- databases
- xml documents