An FPGA implementation of a neural optimization of block truncation coding for image/video compression.
Sherif M. SaifHazem M. AbbasSalwa M. NassarAbdelmonem A. WahdanPublished in: Microprocess. Microsystems (2007)
Keyphrases
- video compression
- block truncation coding
- discrete cosine transforms
- image data
- fpga implementation
- motion compensation
- multiscale
- input image
- motion estimation
- video coding
- image processing algorithms
- motion compensated
- hardware implementation
- three dimensional
- image segmentation
- contrast enhancement
- macroblock
- test images
- compression ratio
- computer vision
- vector field
- image quality
- computational complexity
- image processing