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Circuit level, 32nm, 1-bit MOSSI-ULP adder: power, PDP and area efficient base cell for unsigned multiplier.
S. Vijayakumar
Reeba Korah
Published in:
IEICE Electron. Express (2014)
Keyphrases
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power dissipation
power consumption
levels of abstraction
high speed
cost effective
signal processing
logic circuits
computationally efficient
efficient implementation
circuit design
bit vector
nm technology